1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device is known in which an n-type diffusion layers, a gate insulating film and a gate electrode are formed in a semiconductor substrate. FIG. 1 is a cross section view showing the structure of a conventional semiconductor device. In the semiconductor device, a transistor structure is formed between trench type device isolation sections of a pair. Specifically, the n-type diffusion layers for a source region and a drain region are formed in the surface of the semiconductor substrate having a p-type well layer and a channel dope layer. The gate insulating film is formed on the substrate surface. A gate electrode 3 is formed through the gate insulating film on the substrate surface between the source region and the drain region. Also, electrodes are formed on the source region and the drain region, respectively. Moreover, a silicon oxide film is formed for the gate insulating film and the electrodes to be embedded.
In the semiconductor device having such a structure, a distance between the n-type diffusion layers becomes shorter in accompaniment with the advancement of the miniaturization of wiring lines. A threshold voltage of the gate electrode receives an influence of the n-type diffusion layer with the spread of the n-type diffusion layer. That is, an effective channel length becomes shorter. Consequently, it is difficult to obtain a desirable threshold voltage Vth.
In order to solve this problem, a semiconductor device is known which has an embedded gate electrode shown in FIG. 2. In the semiconductor device shown in FIG. 2, a trench is formed in the semiconductor substrate. The gate electrode is formed to be embedded in the trench through an gate insulating film. By employing the structure that the gate electrode is embedded in the trench, the effective channel length can be controlled in accordance with the depth of the trench. Thus, a higher threshold voltage can be obtained, as compared with a semiconductor device of a planner type shown in FIG. 1.
A semiconductor device of the embedded type as mentioned above is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-306881). An insulating gate type semiconductor device in this first conventional example includes a semiconductor substrate of one conductive type, trenches formed in the semiconductor substrate. The film thickness of a gate insulating film is thinner at a bottom surface of the trench than that at a side of the trench. A gate electrode is formed inside the trench through the gate insulating film. A low concentration diffusion layer of an opposite conductive type is formed to be deeper than the trench in the semiconductor substrate adjacent to the trench, and a high concentration diffusion layer of an opposite conductive type is formed in the low concentration diffusion layer adjacent to the gate electrode and is shallower than the trench.
Also, a single electron tunnel device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-306904). In this second conventional example, a U-shaped trench is formed in a silicon thin line and a thermal oxidization is performed thereon. A portion near the bottom of the U-shaped trench to which stress is applied is slower in oxidization rate than a portion near a trench side wall, and irregularity is consequently generated in an oxide film thickness. A gate electrode is formed on the oxide film, and a positive gate voltage is applied. At this time, electrons are accumulated in the bottom center of the U-shaped trench in which the oxide film is thin, and a tunnel barrier is formed in the portion of a thick oxide film near the trench side wall.
However, when the miniaturization is further advanced, it is difficult to obtain a desirable threshold voltage Vth even in the semiconductor device of the embedded type as mentioned above.
On the other hand, a technique is known in which a section of an upper portion of a trench in which a gate electrode is embedded is rectangular and a section of a lower portion is rounded. Hereinafter, a semiconductor device having such a structure is referred to as a round bottom type. As a semiconductor device of the round bottom type, for example, there is a semiconductor device described in “S-RCAT (Sphere-shaped-Recess-Channel-Array-Transistor) Technology for 70 nm DRAM feature size and beyond” (2005 Symposium on VLSI Technology Digest of Technical Papers: third conventional example). Since the lower portion of the trench is processed to have a circular section, the effective channel length can be made longer than that of a usual gate embedded type transistor. Thus, even if the miniaturization of the transistor is advanced, a desirable threshold voltage can be obtained. Moreover, since the trench bottom has a curved portion, the electric field received from the gate electrode can be made greater in that portion. Therefore, this has a merit that a sub threshold coefficient can be made smaller and an ON current of the transistor can be made greater.
In the semiconductor device of the round bottom type, the fact is known that as a curvature of the trench bottom becomes smaller, the transistor characteristic is degraded. As the curvature becomes smaller, the electric field received from the gate electrode becomes weaker in that portion, and the sub threshold coefficient becomes greater. That is, the curvature of the trench bottom is desired to be greater, and it is desired to have the shape close to a true circle.
In the semiconductor device in the first conventional example, when the semiconductor device of the round bottom type is manufactured, the following process is used. At first, a p-well layer and a channel dope layer are formed, and a hard mask is formed on the semiconductor substrate in which device separation sections are formed, as shown in FIG. 3A. Then, lithography is used to etch a portion for the trench to be formed, and a protection layer is deposited on the substrate having a silicon recess, as shown in FIG. 3B. In succession, an isotropic etching is carried out to form a lower circular portion, as shown in FIG. 3C. Moreover, a side mask (protection layer) formed on the side of the trench and the hard mask are removed, as shown in FIG. 3D. Then, a known method is used to form a gate electrode, as shown in FIG. 3E.
In this way, the shape that is actually formed when the isotropic etching is carried out to form the lower circular section will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram when only the silicon recess portion is shown in FIG. 3B. In the isotropic etching, the regression of a silicon surface appears at the equal distance from the silicon surface. Thus, the sectional shape after the etching is likely to be expanded into a lateral direction, and it is not the true circle, as shown in FIG. 5. Moreover, when the isotropic etching is carried out, a residue (crystal defect) is generated inside the trench, and it becomes difficult to uniformly form the gate insulating film. Thus, in order to form the uniform gate insulating film and further increase the ON current, another process is required.
In conjunction with the above description, Japanese Laid Open Patent Application (JP-P2002-231945A: third conventional example) discloses a technique that carries out a hydrogen annealing process to decrease crystal defects generated inside a trench.
Also, Japanese Laid Open Patent Application (JP-P2003-229479A: fourth conventional example) discloses a technique that carries out the hydrogen annealing process to round trench corner portions. That is, the fourth conventional example describes a method of forming a trench in a surface layer of a semiconductor device, and after removing a protection layer formed on the side wall of the trench and before forming a gate insulating film along the side wall of the trench, carrying out a hydrogen annealing.
Also, Japanese Laid Open Patent Application (JP-P2005-45198A) discloses the structure of a recess gate transistor which has an impurity implantation layer formed in an active region defined in a substrate. In the structure, a first electrode region formed in the active region from a top surface of the active region to a depth which is shallower than to the impurity implantation layer. A gate is extended from a lower portion of the first electrode region to a predetermined depth, passing through the impurity implantation layer and contains a second electrode region larger than a horizontal size of the first electrode region. An insulating film spacer is formed to introduce a difference of the horizontal size between the first and second electrodes into a side wall of the first electrode region. A gate insulation film is formed in the second electrode region to have a constant thickness. Source/drain regions are formed to oppose to each other through the gate with respect to the active region.
However, any of the foregoing conventional examples does not disclose a technique for processing the lower sectional shape of the trench to a shape close to the true circle, while suppressing the residue generated inside the trench.